1. Field of the Invention
The present invention relates to a method for forming a low temperature polysilicon thin film transistor (LTPS TFT), and more particularly, to a method for forming a self-aligned LTPS TFT.
2. Description of the Prior Art
A liquid crystal display is broadly applied to portable electronic apparatuses, such as notebooks and personal digital assistants (PDAs), because of its thin display panel, low power consumption, and low-radiation. As the requirements of high quality displays increase, flat panels with high quality and low price are demanding in the future. An LTPS TFT, which is an actively driving TFT, is one of the important technologies for achieving the goal.
An LTPS TFT-LCD includes at least a transparent substrate, a pixel array region, a scan line driving circuit region, and a data line driving circuit region. The pixel array region comprises a plurality of parallel scan lines, a plurality of parallel data lines, and a liquid crystal molecule layer. Each scan line and each data line define a pixel, and each pixel further comprises a TFT and a storage capacitor. Current LTPS TFT-LCD integrates a standard driving IC in a liquid crystal panel by utilizing LTPS CMOS TFT technologies, thus the size of displays and the cost are reduced.
As shown in FIGS. 1–5, the schematic diagrams demonstrate a method for forming a top gate LPTS CMOS TFT 38 according to the prior art. As shown in FIG. 1, the LTPS CMOS TFT 38 of the prior art comprises an N type low temperature polysilicon thin film transistor (NLTPS TFT) 34 and a P type low temperature polysilicon thin film transistor (PLTPS TFT) 36. The LTPS CMOS TFT 38 of the prior art is formed on a glass substrate 10, and the glass substrate 10 surface comprises a first region I for forming the NLTPS TFT 34, and a second region II for forming the PLTPS TFT 36. In addition, the glass substrate 10 surface further comprises a pixel array region (not shown in FIG. 1) for forming a plurality of NLTPS TFTs 34, which are used to be switches of pixel cells of an LCD, arranged in an array.
According to the prior art, an amorphous silicon (α-Si) layer (not shown in FIG. 1) is formed on the substrate 10, and an annealing process is performed such that the amorphous silicon layer will be recrystallized to a polysilicon layer (not shown in FIG. 1). Then, a first photo-etching process (PEP) is performed to form a patterned polysilicon layer 12 in both the first region I and the second region II of the substrate 10. Afterward, a low temperature deposition process is performed to form a gate insulating (GI) layer 14 to cover the patterned polysilicon layer 12 on the substrate 10, and an aluminum layer (not shown in FIG. 1) is formed over the gate insulating layer 14. Finally, a second photo-etching process is performed to respectively form a gate electrode 16 of the NLTPS TFT 34 and the PLTPS TFT 36 in the aluminum layer of the first region I and the second region II.
As shown in FIG. 2, an implantation process 18 is performed by utilizing the gate electrodes 16 as a mask to implant phosphorous ions into the patterned polysilicon layer 12, which is not covered by the gate electrode 16, to form a plurality of N type lightly doped areas 20. As shown in FIG. 3, a photo resist layer (not shown in FIG. 3) is formed on the substrate 10, and a third photo-etching process is performed to form a patterned photo resist layer 22 in the photo resist layer to cover the second region 11 and the gate electrode 16 of the first region I. Then, an implantation process 24 is performed to implant arsenic ions into the patterned polysilicon layer 12, which is not covered by the patterned photo resist layer 22, to form two N type heavily doped areas 26s and 26d. The N type heavily doped areas 26s and 26d are for respectively being a source electrode and a drain electrode of the NLTPS TFT 34, the lightly doped areas 20, which are located on the side of the N type heavily doped areas 26s and 26d, are used to be lightly doped drains (LDD) of the NLTPS TFT 34, and the patterned undoped polysilicon layer 12, which is below the gate electrode 16 of the NLTPS TFT 34, is for being a channel area of the NLTPS TFT 34.
As shown in FIG. 4, the remaining patterned photo resist layer 22 is removed, and another photo resist layer (not shown in FIG. 4) is formed on the substrate 10. Then, a fourth photo-etching process is performed to form a patterned photo resist layer 28 in the photo resist layer. Afterward, an implantation process 30 is performed by utilizing the patterned photo resist layer 28 and the gate electrode 16 of the PLTPS TFT 36 as a mask to implant boron ions into the patterned polysilicon layer 12, which is not covered by the photo resist layer 28 and the gate electrode 16, such that two P type heavily doped areas 32s and 32d for respectively being a source electrode and a drain electrode of the PLTPS TFT 36 are formed. The patterned undoped polysilicon layer 12, which is below the gate electrode 16, is used to be a channel area of the PLTPS TFT 36. Finally, as shown in FIG. 5, the remaining patterned photo resist layer 28 is removed to form the NLTPS TFT 34 and the PLTPS TFT 36 of the LTPS CMOS TFT 38 of the prior art.
According to the method for forming the LTPS CMOS TFT 38 of the prior art, the gate electrodes 16 of the NLTPS TFT 34 and the PLTPS TFT 36 are first formed, than the N type lightly doped drains 20, the N type source electrode and drain electrode, and the P type source electrode and drain electrode are respectively formed.
Although the above-mentioned method utilizes the gate electrodes 16 as a self-aligned mask to form the N type lightly doped areas 20, another photo resist mask is still required when forming the source electrode and the drain electrode of the NLTPS TFT 34. However, when defining the pattern of the photo resist mask in a photo process by a stepper or a scanner, misalignment or overlap could occur because of human or non-human factors. For example, as shown in FIG. 3, the patterned photo resist layer 22 may shift left, and parts of the patterned polysilicon layer 25 will not be doped. Thus the lightly doped areas 20 will not be equally doped. The asymmetric lightly doped areas 20 not only are incapable of restraining the hot electron effect, but may also generate leakage current of the gate electrode, and further result in breakdown.
Therefore, to form a lightly doped drain with uniform width and avoid a too narrow range between the source electrode and the drain electrode resulting from the misalignment in the photo process is an important topic for study during the LTPS TFT manufacturing processes.